The present invention relates to power transistors of the vertical type, principal examples of which are metal oxide silicon field effect transistors (hereinafter MOSFETs) and insulated gate bipolar transistors (hereinafter IGBTs), which are generally considered to be another type of FET.
Known devices of this type include those having geometries such that multiple base regions are formed within a large drain area, or a large base region is formed to create multiple drain regions. Structures of the first type are exemplified by those disclosed in U.S. Pat. No. 5,008,725, while structures of the second type are exemplified by those disclosed in U.S. Pat. No. 4,823,176.
The type of geometry described in U.S. Pat. No. 4,823,176 offers certain benefits, including the possibility of achieving a relatively high breakdown voltage.
One factor influencing the performance of such FETs, and in particular current handling capability, is channel width. U.S. Pat. No. 4,823,176 describes embodiments in which the multiple drain regions are arranged in a hexagonal lattice pattern, which results in a relatively great channel width. The associated gate electrode has gate segments covering the drain regions and connecting segments connecting together adjacent gate segments.
However, the gate electrode pattern which has previously been proposed, as disclosed in U.S. Pat. No. 4,823,176, is such that it gives the semiconductor device less than an optimum on-resistance. This results from the necessary shape of the connecting segments and the principles employed to construct the gate segment pattern. This will be explained in greater detail below with reference to FIG. 1.
FIG. 1 is a plan view showing a hexagonal FET gate pattern constructed according to the principles disclosed in U.S. Pat. No. 4,823,176. Although that patent does not illustrate a hexagonal gate pattern, the pattern shown in FIG. 1 would be created if a hexagonal pattern were formed in a manner to be a counterpart to the square pattern which is illustrated in the patent.
Such a pattern is composed essentially of gate segments 14, with each adjacent pair of gate segments being connected together by a respective connecting segment 16 to form a hexagonal matrix enclosing individual source contact areas 18. For reasons relating primarily to the manner in which the source electrode (not shown) should be operatively associated with the other transistor regions, gate segments 14 cannot be significantly increased in diameter and connecting segments 16 cannot be substantially increased in width. Thus, with the type of gate pattern shown in FIG. 1, a separate connecting segment is required between each adjacent pair of gate segments, and the regions occupied by the connecting segments can not contain an effective channel portion.